Verification Engineer

Company: YO IT CONSULTING
Location: Austin
Posted on: February 15, 2026

Job Description:

Job Description Job Description Location: Austin, TX Employment Type: Full-Time About the Role We are seeking a skilled Verification Engineer to drive complex RTL design verification across multiple aspects of advanced digital designs. This role offers the opportunity to work on next-generation optical communication systems such as 800G, 1.6T, and beyond , while contributing to the architecture and connectivity innovations powering modern AI and data infrastructure. Responsibilities Plan, architect, and execute verification strategies based on design specifications Develop and maintain SystemVerilog/UVM verification environments Define and implement functional and corner-case coverage metrics Debug RTL functionality and collaborate closely with design and architecture teams Analyze coverage results and drive coverage closure Participate in design reviews, test plan creation, regression execution, and verification sign-off Required Qualifications 5 years of experience in digital/RTL engineering Minimum 3 years of hands-on experience in design verification Strong knowledge of VLSI verification flows, concepts, and industry-standard tools Experience completing at least one full block or system verification cycle Hands-on experience with SystemVerilog UVM (or Specman/eRM, SystemC equivalents) Strong debugging and waveform analysis skills Nice to Have Experience in datapath or protocol-level verification (Ethernet or other high-speed interfaces) Experience writing advanced functional, code, and corner-case coverage Exposure to mixed-signal or analog/digital verification Strong communication and documentation skills

Keywords: YO IT CONSULTING, San Marcos , Verification Engineer, IT / Software / Systems , Austin, Texas